Electronic circuit design method, simulation apparatus and computer-readable storage medium
US7086018B2 · kind B2 · utility
188Cited by
6References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Apr 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit designing method analyzes noise with respect to a wiring pair, and automatically corrects the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.