Programmable logic device partitioning method for application specific integrated circuit prototyping
US7086025B1 · kind B1 · utility
8Cited by
16References
10Claims
0Family size
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Key dates
| Filing date | Oct 23, 2003 |
| Grant date | Aug 1, 2006 |
| Priority date | — |
| Expiry date | Jul 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/181
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The interconnect pin count between field programmable gate arrays (FPGAS) used in prototyping an application specific integrated circuit (ASIC) is reduced without compromising the prototyping by using serial links between the FPGAs. A block A of the ASIC is programmed in a first FPGA. A block B of the ASIC is programmed in a second FPGA. Blocks A and B are identical between ASIC and FPGA implementations. Block A communicates with block B via two interconnected wrappers, which are, in this example, serial COM wrappers connected by a serial link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.