LSI device having core and interface regions with SOI layers of different thickness
US7087967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Aug 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.