Programmable logic device with flexible memory allocation and routing
US7088134B1 · kind B1 · utility
43Cited by
1References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 6, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Nov 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.