Symmetric and non-stacked XOR circuit
US7088138B2 · kind B2 · utility
4Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Oct 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CML XOR logic circuit is provided that includes a pair of pull-up transistors, a pair of current source transistors and a logic switch network coupled between the pull-up transistors and the current source transistors. The logic switch network including a plurality of transistors divided into a first branch, a second branch and a third branch. A tail current flows through the first branch, the second branch or the third branch based on at least two input signals to the plurality of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.