Sample and hold circuit and bootstrapping circuits therefor
US7088148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.