Delay interpolation in a ring oscillator delay stage
US7088191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0322
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.