Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays
US7088638B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2005 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Mar 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A global and local read control synchronization method and system are provided for a memory array configured with multiple memory subarrays. Address signals are decoded to activate based thereon subarray select signals and a cumulative subarray select signal. The cumulative subarray select signal goes active whenever a subarray select signal goes active, and therefore, each pulse of the cumulative subarray select signal is synchronous with one pulse of the subarray select signals. Local read control signals for the multiple memory subarrays are obtained employing the subarray select signals, and at least one global read control signal for the memory array is obtained employing the cumulative subarray select signal. In one example, the memory array has a hierarchical bitline architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.