Method for optimizing utilization of a double-data-rate-SDRAM memory system
US7089369B2 · kind B2 · utility
101Cited by
1References
22Claims
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Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Dec 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.