Apparatus and method to reduce memory footprints in processor architectures
US7089390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Jul 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/44557
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.