Method and apparatus for controlling program instruction completion timing for processor verification
US7089406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Oct 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.