Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution
US7089408B2 · kind B2 · utility
7Cited by
5References
12Claims
0Family size
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Key dates
| Filing date | May 12, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Jun 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to re-fetch operand data lost for instructions with operands greater than eight bytes in length due to line invalidation due to storage update from a single or plurality of processors in a multiprocessor computer system using microprocessors that perform out of order operand fetch with respect to sequential program order in which it is not possible or desirable to kill the execution of the instruction when the storage access rules require that it appear that the operand data is accessed in program execution order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.