Adaptive memory module
US7089412B2 · kind B2 · utility
51Cited by
6References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Apr 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module contains a plurality of memory devices and receives control signals over a memory bus for accessing the memory devices. An adaptive buffering mechanism includes unregistered logic to electrically isolate the received control signals from one or more control drive signals. Register logic substantially synchronizes the control drive signals to a system clock to produce clocked control drive signals. A mode selection mechanism selectively outputs either the control drive signals or the clocked control drive signals to access the memory devices in accordance with a mode selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.