Managing multiple processor performance states
US7089430B2 · kind B2 · utility
22Cited by
13References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Aug 6, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a performance information associated with a processor is read. A processor performance table that corresponds to the performance information is located. The performance table includes a plurality of performance parameters to control performance of the processor. A performance state (PS) structure is updated using one of the processor performance table and a default table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.