Power saving method and arrangement for a configurable processor array
US7089436B2 · kind B2 · utility
2Cited by
12References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2001 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | May 22, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and arrangement for reducing power consumption in an M row×N column array of processing cells. A row mask register masks individual cells in each row for being enabled. A column mask register masks individual cells in each column for being enabled. The combination of the row mask register signal and column mask register signal enables or disables each cell of the array. Enabled cells are activated to execute an operation or function, while disabled cells a prevented from consuming dynamic power. Depending on the application and enabled cells thereby, power consumption is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.