Framework for hierarchical VLSI design
US7089511B2 · kind B2 · utility
26Cited by
7References
27Claims
0Family size
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Key dates
| Filing date | Dec 10, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on the hierarchical very large scale integrated design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.