Integrated circuit design for signal integrity, avoiding well proximity effects
US7089513B2 · kind B2 · utility
101Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Mar 19, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Oct 20, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.