High speed software driven emulator comprised of a plurality of emulation processors with a method to allow memory read/writes without interrupting the emulation
US7089538B1 · kind B1 · utility
1Cited by
14References
4Claims
0Family size
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Key dates
| Filing date | Sep 6, 2000 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Aug 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cycle, the memory controller disables the main data memories on the module, and allows the maintenance bus to read or write data to these memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.