High voltage device embedded non-volatile memory cell and fabrication method
US7091535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2004 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Mar 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.