Recess transistor (TR) gate to obtain large self-aligned contact (SAC) open margin
US7091540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2003 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Oct 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.