Circuit power reduction using micro-electromechanical switches
US7091765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides micro-electromechanical switch (MEM) based designs for reducing the power consumption of logic blocks (e.g., latches) by isolating the logic blocks when they are non-operational. A power reduction circuit in accordance with the present invention comprises a logic block and at least one micro-electromechanical (MEM) switch for selectively disabling the logic block. MEM switches are provided for selectively: disconnecting the logic block from power; disconnecting the logic block from ground; providing a bypass line around the logic block; disconnecting an output of the logic block; and/or disconnecting an input of the logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.