Calibration of analog to digital converter by means of multiplexed stages
US7091891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2004 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Apr 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved pipelined analog to digital converter that facilitates calibration for non-linearity errors and a method for obtaining calibration values. The analog to digital converter has a calibration mode in which the output bits for stages in the pipeline can be coupled to output pins of the device. Device pins that are used in normal operating mode to output the most significant bits of the ADC output are used in calibration mode to make available output bits of a pipeline stage being calibrated. A calibration method takes advantage of the outputs of the stages being directly observable to compute calibration values. The output bits of a pipeline stage are monitored as the analog input to the ADC is increased. A change in these bits identifies a subrange boundary. Errors are measured for values immediately above and immediately below each subrange boundary and used to compute correction factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.