Organic light-emitting diode display
US7091940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/043
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A technique to reduce the rate of increase in threshold voltage, i.e. degradation, of an amorphous silicon TFT driving an OLED. A first supply voltage is supplied to a drain of the TFT when a first control voltage is applied to a gate of the TFT to activate the TFT and drive the OLED. However, a second, lower supply voltage is supplied to the drain of the TFT when a second control voltage is applied to the gate of the TFT to deactivate the TFT and turn off the OLED, whereby a voltage differential between the drain and the source when the second control voltage is applied to the gate is substantially lower said first supply voltage. This reduces degradation of the TFT. According to one feature of the present invention, when the TFT is turned off by the absence of voltage applied to its gate, the voltage at the drain of the TFT is reduced to approximately zero to minimize the voltage differential between the drain and the source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.