Memory device
US7092278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2005 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data reading can be easily and precisely performed by setting specific conditions in writing into a selected memory cell. A memory cell has a structure, in which an interelectrode material layer is sandwiched between a first electrode and a second electrode. Data is stored by a change in a resistance value between the first electrode and the second electrode. The resistance value when a memory element is in a high resistance state is expressed as R_mem_high; the resistance value when the memory element is in a low resistance state is expressed as R_mem_low1; the resistance value of a load circuit is expressed as R_load; the reading voltage is expressed as Vread by setting the voltage of a second power supply line to the reference voltage; and the threshold voltage is expressed as Vth_critical. In writing data into the memory cell, the low resistance state is created so that these parameters satisfy specific relations. The load circuit is formed by an element having the same structure as of the memory element of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.