Method and apparatus for reducing soft error rate in SRAM arrays using elevated SRAM voltage during periods of low activity
US7092281B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2005 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Apr 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage supplied to an SRAM (static random access memory) in an electronic system is controlled responsive a level of activity in the electronic system. If the level of activity is higher, the voltage is kept lower; if the level of activity, the voltage is increased, reducing soft error rate in the SRAM. For example, one indicator of the level of activity is how frequently the SRAM is accessed. If the SRAM is accessed less frequently, a higher voltage value is used to supply the SRAM than if the SRAM is accessed more frequently. A higher voltage provides a lower soft error rate (SER), but increases power dissipation. The SRAM dissipates less switching power when it is infrequently used and therefore a higher voltage value can be supplied to the SRAM during such times of infrequent use without causing excessive power dissipation by the electronic system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.