System and method for recovering and deserializing a high data rate bit stream
US7092466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2002 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Sep 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.