Method and apparatus for minimizing differential power attacks on processors
US7092523B2 · kind B2 · utility
11Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2001 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Dec 15, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of masking a cryptographic operation using a secret value, comprising the steps of dividing the secret value into a plurality of parts; combining with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and utilizing each of the individual parts in the operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.