Method and coding means for error-correction utilizing concatenated parity and turbo codes
US7093179B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2002 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Sep 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for encoding and decoding data using an overall code comprising an outer parity-check and an inner parallel concatenated convolutional, or turbo code. The overall code provides error probabilities that are significantly lower than can be achieved by using turbo codes alone. The output of the inner code can be punctured to maintain the same turbo code rate as the turbo code encoding without the outer code. Multiple parity-check codes can be concatanated either serially or in parallel as outer codes. Decoding can be performed with iterative a posteriori probability (APP) decoders or with other decoders, depending on the requirements of the system. The parity-check code can be applied to a subset of the bits to achieve unequal error protection. Moreover, the techniques presented can be mapped to higher order modulation schemes to achieve improved power and bandwidth efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.