Model-based logic design
US7093224B2 · kind B2 · utility
2Cited by
106References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2001 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Aug 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.