Internal voltage reference for memory interface
US7095245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2003 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Jan 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include a memory controller to interface to memory. In one embodiment, the memory controller includes a pull-up calibration terminal to couple to an external pull-up resistor, a pull-down calibration terminal to couple to an external pull-down resistor, a voltage reference node, a first switch coupled between the pull-up calibration terminal and the voltage reference node, and a second switch coupled between the pull-down calibration terminal and the voltage reference node. The first switch and the second switch may be selectively closed to generate an internal voltage reference on the voltage reference node in a normal mode that may be used for comparison with an input signal to receive data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.