Configuring FPGAs and the like using one or more serial memory devices
US7095247B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2004 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | May 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17748
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration data stored in the memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the FPGA. In one embodiment, the FPGA has an Serial Peripheral Interface (SPI) that is connected to the SPI interface of each of one or more SPI serial flash PROMs operating as boot PROMs. When there are two or more boot PROMs, each PROM stores a portion of the FPGA's configuration data and the FPGA interleaves the data from multiple boot PROMs to generate a serial configuration data bitstream. The present invention enables boot PROMs having different sizes and/or storing different amounts of configuration data to be simultaneously connected to an FPGA to support efficient configuration architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.