Fast low drop out (LDO) PFET regulator circuit
US7095257B2 · kind B2 · utility
6Cited by
5References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 7, 2004 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Aug 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A low dropout (LDO) PFET regulator circuit is disclosed for operating in two modes of operation. For higher supply voltage potentials the LDO PFET regulator circuit operates normally, as supply voltage potential drops, the LDO PFET regulator operates in a second mode of operation where a decision circuit determines whether to supply a first boost current thereto in order to compensate for the reduced transimpedance of the first PFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.