Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
US7095661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2004 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.