Electrical fuse control of memory slowdown
US7095671B2 · kind B2 · utility
4Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2005 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Nov 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.