Method for decoding biphase signals

US7095807B2 · kind B2 · utility

Assignee

• Micronas GmbH · DE

Inventors

• Carsten Noeske · Glottertal, DE
• Matthias Vierthaler · Denzlingen, DE
• Thomas Hilpert · Denzlingen, DE

Key dates

• Filing date: Jun 24, 2002
• Grant date: Aug 22, 2006
• Expiry date: May 23, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04H2201/13
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d1) is derived. From this, associated bit combinations (St1, St2; Stp) are determined, and a decision is made as to whether the respective bit combination (St1, St2; Stp) is a valid combination (Sg1, Sg2; Sgp) or an erroneous one (Sf1, Sf2; Sfp). Probability values (Sw1, Sw2; Swp) are determined that decide which parts of the erroneous bit combination (Sf1, Sf2; Sfp) are probably true and/or which are probably false. Next, a corrected bit combination (Sk1, Sk2; Skp) is formed from the existing information. Finally, a second digital signal (d2) is generated as an output signal, whose data states are formed either from the valid bit combination (Sg1, Sg2; Sgp) or from the corrected bit combination (Sk1, Sk2; Skp).