Multiprocessor array
US7096177B2 · kind B2 · utility
2Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Jan 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.