Supercharge message exchanger
US7096296B2 · kind B2 · utility
1Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2004 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.