Reduced cardbus controller
US7096298B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2003 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Oct 27, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cardbus controller is provided that reduces signal count and board area. In one exemplary embodiment, the controller is adapted to multiplex selected signals in a two PC Card system so that signal lines are not repeated. The selected signals may include common signals between two PC Cards. The controller may also include early detection circuitry, arbitration circuitry and power management circuitry to more effectively operate two PC Cards. In other exemplary embodiments, the invention provides a method of reducing the chip area of a PC Card controller integrated circuit by mapping an internal IDSEL signal to an external address line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.