Manufacturing method of semiconductor integrated circuit device
US7098111B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Sep 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
Abstract
A manufacturing technology of a MOSFET having a shallow junction and a source and drain of a low resistance is provided. After having ion-implanted an As on the surface of a p type well forming a gate electrode, a surface protection layer and an energy absorber layer are deposited on a substrate. When the surface of the substrate is irradiated by a YAG laser beam of the wavelength of 1064 nm for one nano second to 999 nano seconds, a heat absorbed by the energy absorber layer is transmitted to the substrate in an ultra short time, and heats its surface to a melting temperature, and therefore, the impurity is activated, and an extension region of a low resistance is formed in an extremely shallow region of about 20 nm in depth from the surface of the p type well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.