Thin film transistor array panel and a method for manufacturing the same
US7098480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2002 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136222
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer. Next, the exposed portions of conductor layer are removed by wet etch or dry etch, and thereby the underlying ohmic contact layer is exposed. Then the exposed ohmic contact layer and the underlying semiconductor layer are removed by…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.