Semiconductor package and packaging method using flip-chip bonding technology
US7098535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor package and packaging method using a flip-chip bonding technology is disclosed. In the semiconductor package and packaging method, the microelement array of a micro-device, for example, the micromirror array of a light modulator having micromirrors that are hyperfine elements, is sealed from the outside using flip-chip bonding technology. Thus, the microelement array is protected from the outside. The packaging method executes the packaging process using only the flip-chip bonding technology, without a wire-bonding technology, at a wafer level instead of a conventional individual semiconductor device level, thus increasing the bonding process efficiency. Furthermore, the electrode array pattern for supplying both electricity and control signals to the microelement array does not pass through a hermetic sealing layer, thus ensuring a well-sealed semiconductor package. The electrode array pattern is also finely formed to correspond to the microelement array which is extremely finely formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.