Interconnect method for directly connected stacked integrated circuits
US7098541B2 · kind B2 · utility
33Cited by
9References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 19, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | May 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and related configuration for stacking and interconnecting multiple identical integrated circuit semiconductor die. A die designed in accordance with the present invention can be directly interconnected with other identical die by placing a second die on a first die. The second die is substantially identical to the first die and has a rotation with respect to the first die. A plurality of electrical interconnections on the first die are contacted with a plurality of electrical interconnections on the second die, forming electrical interconnects between adjacent stacked dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.