Semiconductor device and method of enveloping an integrated circuit
US7098545B2 · kind B2 · utility
0Cited by
13References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2002 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Nov 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package of a semiconductor device comprising an integrated circuit (10) generally comprises an inner layer (21) and an outer layer (16), which layers (16,21) have a mutual interface (24). An improved stability of the package is realized in that the interface (24) encloses a delamination area (22), which area (22) is isolated from any bond pads (18) of the integrated circuit (10). The delamination area (22) may be created by a pattern-wise activation of a surface of the inner layer (21). A quantity of a curable polymer may be disposed on this surface to achieve this.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.