High speed switch
US7098684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Jun 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/04113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.