Overvoltage tolerant input buffer
US7098694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Jan 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied. Another embodiment has two N-channel devices (M12, M13) coupled in series with each other and one of the N-channel devices (M13) being configured in a “turned off” position, by coupling the source and gate terminals to a ground voltage (VSS) and providing the supply voltage (VDD) at the gate terminal of another N-channel device (M12), whereby the device M12 protects the device M13 from overvoltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.