Low voltage high-speed differential logic devices and method of use thereof
US7098697B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | May 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/212
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%–50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.