Reduced chop rate analog to digital converter system and method
US7098823B2 · kind B2 · utility
37Cited by
8References
25Claims
0Family size
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Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.