Semiconductor memory device and method for masking predetermined area of memory cell array during write operation
US7099207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2005 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Apr 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell array, including at least one of a plurality of memory cells storing program data received from a flash memory, a row address buffer, which receives a row address signal in response to a first strobe signal, and a column address buffer, which receives a column address signal in response to a second strobe signal. The device further includes a write protection circuit, enabled/disabled in response to a first control signal, the write protection circuit outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals when enabled, and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array, corresponding to the decoded column address signal, or disables the column selection lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.