Systems, methods and devices for providing variable-latency write operations in memory devices
US7099215B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Mar 10, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A memory system includes storage cells, a respective one of which is configured to store a fixed charge therein when a write voltage applied thereto is above a predetermined threshold voltage and to discharge the fixed charge therefrom when the write voltage applied thereto is below the threshold voltage. The storage cells may be charged and/or discharged at a latency that is a function of a voltage differential between the write voltage and the threshold voltage. A variable-latency write circuit for the storage cells is configured to dynamically vary the voltage differential between the write voltage and the threshold voltage to provide a variable-latency write operation that stores the fixed charge therein or discharges the fixed charge therefrom. Related methods are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.