Method and system for buffering a data packet for transmission to a network
US7099345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2001 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Jul 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.